Zilog Z80 - Z80 Computer

The Z80 CPU is an 8-bit based microprocessor. It was introduced by Zilog in 1976 as the startup company's first product. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his then-11 employees at Zilog from early 1975 until March 1976, when the first fully working samples were delivered. With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two years.

The Zilog Z80 was a software-compatible extension and enhancement of the Intel 8080 and, like it, was mainly aimed at embedded systems. According to the designers, the primary targets for the Z80 CPU (and its optional support and peripheral ICs) were products like intelligent terminals, high end printers and advanced cash registers as well as telecom equipment, industrial robots and other kinds of automation equipment. The Z80 was officially introduced on the market in July 1976 and came to be widely used also in general desktop computers using CP/M and other operating systems as well as in the home computers of the 1980s. It was also common in military applications, musical equipment, such as synthesizers, and in the computerized coin operated video games of the late 1970s and early 1980, the arcade machines or video game arcade cabinets.

The Z80 was one of the most commonly used CPUs in the home computer market from the late 1970s to the mid-1980s. Zilog licensed the Z80 to the US-based Synertek and Mostek, which had helped them with initial production, as well as to a European second source manufacturer, SGS. The design was copied also by several Japanese, East European and Russian manufacturers. This enabled the Z80 to gain acceptance in the world market since large companies like NEC, Toshiba, Sharp, and Hitachi, started to manufacture the device (or their own Z80-compatible designs). In recent decades Zilog has refocused on the ever-growing market for embedded systems (for which the original Z80 and the Z180 were designed) and the most recent Z80-compatible microcontroller family, the fully pipelined 24-bit eZ80 with a linear 16Â MB address range, has been successfully introduced alongside the simpler Z180 and Z80 products.

History

Homebrew Z80 computer v2 with CP/M - Unfinished z80 computer. The part of disassemble and schematics are from 3:02.

The Z80 came about when physicist Federico Faggin left Intel at the end of 1974 to found Zilog with Ralph Ungermann. At Fairchild Semiconductor, and later at Intel, Faggin had been working on fundamental transistor and semiconductor manufacturing technology. He also developed the basic design methodology used for memories and microprocessors at Intel and led the work on the Intel 4004, the 8080 and several other ICs. Masatoshi Shima, the principal logic and transistor level-designer of the 4004 and the 8080 under Faggin's supervision, also joined the Zilog team.

By March 1976, Zilog had developed the Z80 as well as an accompanying assembler based development system for its customers, and by July 1976, this was formally launched onto the market. (Some of the Z80 support and peripheral ICs were under development at this point, and many of them were launched during the following year.)

Early Z80s were manufactured by Synertek and Mostek, before Zilog had its own manufacturing factory ready, in late 1976. These companies were chosen because they could do the ion implantation needed to create the depletion-mode MOSFETs that the Z80 design used as load transistors in order to cope with a single 5 Volt power supply.

Faggin designed the instruction set to be binary compatible with the Intel 8080 so that most 8080 code, notably the CP/M operating system and Intel's PL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the microarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and layout people. CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. Faggin worked 80 hours a week in order to meet the tight schedule given by the financial investors, according to himself.

The Z80 offered many improvements over the 8080:

An enhanced instruction set including single-bit addressing, shifts/rotates on memory and registers other than the accumulator, rotate instructions for BCD number strings in memory, program looping, program counter relative jumps, block copy, block input/output (I/O), and byte search instructions. The Z80 also incorporated an overflow flag and had better support for signed 8- and 16-bit arithmetics.
New IX and IY index registers with instructions for direct base+offset addressing
A better interrupt system
- A more automatic and general vectorized interrupt system, mode 2, primarily intended for Zilog's line of counter/timers, DMA and communications controllers, as well as a fixed vector interrupt system, mode 1, for simple systems with minimal hardware (with mode 0 being the 8080-compatible mode).
- A non maskable interrupt (NMI) which can be used to respond to power down situations or other high priority events (and allowing a minimalistic Z80 system to easily implement a two-level interrupt scheme in mode 1).
- Two separate register files, which could be quickly switched, to speed up response to interrupts such as fast asynchronous event handlers or a multitasking dispatcher. Although they were not intended as extra registers for general code, they were nevertheless used that way in some applications.
Less hardware required for power supply, clock generation and interface to memory and I/O
- Single 5-volt power supply (the 8080 needed -5Â V/+5Â V/+12Â V).
- Single-phase 5Â V clock (the 8080 needed a high-amplitude (9 to 12 volt) non-overlapping two-phase clock).
- A built-in DRAM refresh mechanism that would otherwise have to be provided by external circuitry.
- Non-multiplexed buses (the 8080 had state-signals multiplexed onto the data bus).
A special reset function which clears only the program counter so that a single Z80 CPU could be used in a development system such as an in-circuit emulator.

The Z80 took over from the 8080 and its offspring, the 8085, in the processor market, and became one of the most popular 8-bit CPUs. Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, and other features which allowed systems to be built with fewer support chips (Z80 embedded systems typically use static RAM and hence do not need this refresh).

For the original NMOS design, the specified upper clock frequency limit increased successively from the introductory 2.5Â MHz, via the well known 4Â MHz (Z80A), up to 6 (Z80B) and 8Â MHz (Z80H). CMOS versions were also developed with specified upper frequency limits ranging from 4Â MHz up to 20Â MHz for the version sold today. The CMOS versions also allowed low-power sleep with internal state retained, having no lower frequency limit. The fully compatible derivatives HD64180/Z180 and eZ80 are currently specified for up to 33 and 50Â MHz respectively.

Design

Thomas Scherrer Z80-Family Official Support Page. Source : www.z80.info

Programming model and register set

The programming model and register set are fairly conventional, ultimately based on the register structure of the Datapoint 2200 (which the related 8086 family also inherited). The Z80 was designed as an extension of the 8080, created by the same engineers, which in turn was an extension of the 8008. The 8008 was basically a PMOS implementation of the TTL-based CPU of the Datapoint 2200.

This original design allowed register H and L to be paired into a 16-bit address register HL In the 8080 this pairing was generalized into BC and DE, while HL also became usable as a 16-bit accumulator. The 8080 also introduced the important 8-bit immediate data mode for accumulator operations and immediate 16-bit data for HL, BC and DE loads. Furthermore, direct 16-bit copying between HL and memory was now possible, using a direct address. The Z80 orthogonalized this a bit further by making all 16-bit register pairs (including IX and IY) more general purpose, with 16-bit copying directly to and from memory.

The 16-bit IX and IY registers in the Z80 are primarily intended as base address-registers, where a particular instruction supplies a constant offset, but they are also usable as 16-bit accumulators, among other things. The Z80 also introduces a new signed overflow flag and complements the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for signed 16-bit arithmetics.

The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80, where the processor can quickly switch from one bank to the other; a feature useful for speeding up responses to single-level, high-priority interrupts. A similar feature was present in the Datapoint 2200 but was never implemented at Intel. The dual register-set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers. According to one of the designers, Masatoshi Shima, the market focus was on high performance printers, high-end cash registers, and intelligent terminals, although Ralph Ungermann also saw other opportunities, such as computers. The two register sets also turned out to be quite useful for heavily optimized manual assembly-language coding, such as for floating point arithmetics or home computer games.

Registers

As on the 8080, 8-bit registers are typically paired to provide 16-bit versions. The 8080 compatible registers are:

AF: 8-bit accumulator (A) and flag bits (F) carry, zero, minus, parity/overflow, half-carry (used for BCD), and an Add/Subtract flag (usually called N) also for BCD
BC: 16-bit data/address register or two 8-bit registers
DE: 16-bit data/address register or two 8-bit registers
HL: 16-bit accumulator/address register or two 8-bit registers
SP: stack pointer, 16 bits
PC: program counter, 16 bits

The new registers introduced with the Z80 are:

IX: 16-bit index or base register for 8-bit immediate offsets or two 8-bit registers
IY: 16-bit index or base register for 8-bit immediate offsets or two 8-bit registers
I: interrupt vector base register, 8 bits
R: DRAM refresh counter, 8 bits (msb does not count)
AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )
BC', DE' and HL': alternate (or shadow) registers (toggled in and out with EXX)
Four bits of interrupt status and interrupt mode status

There is no direct access to the alternate registers; instead, two special instructions, EX AF,AF' and EXX, each toggles one of two multiplexer flip-flops. This enables fast context switches for interrupt service routines: EX AF, AF' may be used alone, for really simple and fast interrupt routines, or together with EXX to swap the whole BC, DE, HL set. This is still several times as fast as pushing the same registers on the stack. Slower, lower priority, or multi level interrupts normally use the stack to store registers, however.

The refresh register, R, increments each time the CPU fetches an opcode (or opcode prefix) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes. It has also been employed as a "hardware" counter in some designs; an example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).

The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to the CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine. The pointer identifies a particular peripheral chip or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in a system not using interrupts) it can be used as simply another 8-bit data register.

The instructions LD A,R and LD A,I affect the Z80 flags register, unlike all the other LD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to the current state of the IFF2 flip-flop.

Z80 assembly language

Datapoint 2200 and Intel 8008

The first Intel 8008 assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the added addressing possibilities in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible; however, the 8008 was binary compatible with the Datapoint 2200).

In this process, the mnemonic L, for LOAD, was replaced by various abbreviations of the words LOAD, STORE and MOVE, intermixed with other symbolic letters. The mnemonic letter M, for memory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding operand, while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on).

Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions. The Z80 syntax uses parentheses around an expression to indicate that the value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address

New syntax

Because Intel claimed a copyright on their assembly mnemonics, a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used:

All registers and register pairs are explicitly denoted by their full names
Parentheses are consistently used to indicate "memory contents at" (constant address or variable pointer dereferencing) with the exception of some jump instructions.
All load and store instructions use the same mnemonic name, LD, for LOAD (a return to the simplistic Datapoint 2200 vocabulary); other common instructions, such as ADD and INC, use the same mnemonic regardless of addressing mode or operand size. This is possible because the operands themselves carry enough information.

These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,(1234).

Apart from naming differences, and despite a certain discrepancy in basic register structure, the Z80 and 8086 syntax are virtually isomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be assembled into 8086 object code using a special assembler or translated to 8086 assembly language by a translator program.

Instruction set and encoding

The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction"); the four remaining codes are used extensively as opcode prefixes: CB and ED enable extra instructions and DD or FD selects IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080 (allowing operation of most 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories:

8-bit arithmetic and logic operations
16-bit arithmetic
8-bit load
16-bit load
Bit set, reset, and test
Call, return, and restart
Exchange, block transfer, and search
General purpose arithmetic and CPU control
Input and output
Jump
Rotate and shift

No multiply instruction is available in the original Z80. Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most of the flag-changing properties of the 8080 were copied.

The Z80 has six new LD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairsâ€"unlike the 8080. As on the 8080, load instructions do not affect the flags (except for the special purpose I and R register loads). A quirk (common with the 8080) of the register-to-register load instructions is that each of the 8-bit registers can be loaded from themselves (e.g. LD A,A). This is effectively a NOP.

Unlike the 8080, the Z80 can jump to a relative address using a signed 8-bit displacement. Only the Zero and Carry flags can be tested for these new two-byte JR instructions.

A two-byte instruction specialized for program looping is new to the Z80. DJNZ (Decrement Jump if Non-Zero) takes a signed 8-bit displacement as an immediate operand. The B register is decremented. If the result is nonzero then program execution jumps relative to the address of the PC plus the displacement. The flags remain unaltered. To perform an equivalent loop on an 8080 would require separate decrement and jump (to a two-byte absolute address) instructions, and the flag register would be altered.

The index register (IX/IY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records) or at fixed offsets relative a variable base address (as in recursive stack frames) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g. 19 T-states to access one indexed memory location vs. as little as 11 to access the same memory using HL and INCrement it to point to the next). Thus, for simple or linear accesses of data, IX and IY tend to be slower. Still, they may be useful in cases where the 'main' registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80; nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage.

The 10-year-newer microcoded Z180 design could initially afford more "chip area", permitting a slightly more efficient implementation (using a wider ALU, among other things); similar things can be said for the Z800, Z280, and Z380. However, it was not until the fully pipelined eZ80 was launched in 2001 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle.

Undocumented instructions

The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality, they were implemented as a pair of 8-bit registers, in the same fashion as the HL register, which is accessible either as 16 bits or separately as the High and Low registers. Even the binary opcodes (machine language) were identical, but preceded by a new opcode prefix. Zilog published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. As an example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix, DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar to LD H,(IX+d) which make use of both the HL and IX or IY registers in the same instruction; in this case the DD prefix is only applied to the (IX+d) portion of the instruction.

There are several other undocumented instructions as well. Undocumented or illegal opcodes are not detected by the Z80 and have various effects, some of which are useful. However, as they are not part of the formal definition of the instruction set, different implementations of the Z80 are not guaranteed to work the same way for every undocumented opcode.

Bugs

The OTDR instruction doesn't conform to the Z80 documentation. Both OTDR and OTIR are supposed to leave the carry C unaffected. OTIR functions correctly; however, during the execution of the OTDR instruction, the carry takes the results of a spurious compare between the accumulator and what has last been output by the OTDR instruction.

Example code

The following Z80 assembly source code is for a subroutine named memcpy that copies a block of data bytes of a given size from one location to another. Important: the example code does not handle a certain case where the destination block overlaps the source; a fatal bug. The sample code is extremely inefficient, intended to illustrate various instruction types, rather than best practices for speed. In particular, the Z80 has a single instruction that will execute the entire loop (LDIR). The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. Note that the assembled code is binary-compatible with the Intel 8080 and 8085 CPUs.

Instruction execution

Each instruction is executed in steps that are usually termed machine cycles (M-cycles), each of which can take between three and six clock periods (T-cycles). Each M-cycle corresponds roughly to one memory access or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap.

The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3, 4, 5 or 6 T-cycles depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2â€"3 times higher). It does not imply tighter requirements on memory access times, since a high resolution clock allows more precise control of memory timings and so memory can be active in parallel with the CPU to a greater extent, allowing more efficient use of available memory bandwidth.

One central example of this is that, for opcode fetch, the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal lasts for a relatively larger part of the typical instruction execution time than in a design such as the 6800, 6502, or similar, where this period would typically last typically 30-40% of a clock cycle. With memory chip affordability (i.e. access times around 450-250Â ns in the 1980s) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80.

Memory was generally slow compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding SRAM; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.

The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. During refresh the contents of the Interrupt register I are sent out on the upper half of the address bus.

Compatible peripherals

Zilog introduced a number of peripheral parts for the Z80, which all supported the Z80's interrupt handling system and I/O address space. These included the Counter/Timer Channel (CTC), the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were produced.

Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 had a separate control line and address space for I/O instructions. While some Z80-based computers such as the Osborne 1 used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals.

The Z80 was officially described as supporting 16-bit (64Â KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16 bit BC register on the address bus; OUT (n),A and IN A,(n) places the contents of the A register on b8-b15 of the address bus and n on b0-b7 of the address bus. A designer could choose to decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the Amstrad CPC/PCW and ZX81.

Second sources and derivatives

A tiny Z80 based computer. Source : www.vaxman.de

Second sources

Mostek, who produced the first Z80 for Zilog, offered it as second-source as MK3880. SGS-Thomson (now STMicroelectronics) was a second-source, too, with their Z8400. Sharp and NEC developed second sources for the NMOS Z80, the LH0080 and ÂµPD780C respectively. The ÂµPD780C was used in the Sinclair ZX80 and ZX81, original versions of the ZX Spectrum, and several MSX computers, and in musical synthesizers such as Oberheim OB-8 and others. The LH0080 was used in various home computers and personal computers made by Sharp and other Japanese manufacturers, including Sony MSX computers, and a number of computers in the Sharp MZ series.

Toshiba made a CMOS-version, the TMPZ84C00, which is believed (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z80-chips made by GoldStar (alias LG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) in NMOS and CMOS made by ROHM Electronics.

In East Germany, an unlicensed clone of the Z80, known as the U880, was manufactured. It was very popular and was used in Robotron's and VEB Mikroelektronik MÃ¼hlhausen's computer systems (such as the KC85-series) and also in many self-made computer systems. In Romania another unlicensed clone could be found, named MMN80CPU and produced by Microelectronica, used in home computers like TIM-S, HC, COBRA.

Also, several clones of Z80 were created in the Soviet Union, notable ones being the T34BM1, also called ÐšÐ 1858Ð'Ðœ1 (parallelling the Russian 8080-clone KR580VM80A). The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in the late 1980s, there are many more T34BM1s than ÐšÐ 1858Ð'Ðœ1s.

Derivatives

Compatible with the original Z80

Hitachi developed the HD64180, a microcoded and partially dynamic Z80 in CMOS, with on chip peripherals and a simple MMU giving a 1Â MB address space. It was later second sourced by Zilog, initially as the Z64180, and then in the form of the slightly modified Z180 which has bus protocol and timings better adapted to Z80 peripheral chips. Z180 has been maintained and further developed under Zilog's name, the newest versions being based on the fully static S180/L180 core with very low power draw and EMI (noise).
Toshiba developed the 84 pin Z84013 / Z84C13 and the 100 pin Z84015 / Z84C15 series of "intelligent peripheral controllers", basically ordinary NMOS and CMOS Z80 cores with Z80 peripherals, watch dog timer, power on reset, and wait state generator on the same chip. Manufactured by Sharp as well as Toshiba. These products are today second sourced by Zilog.
The 32-bit Z80 compatible Zilog Z380, introduced 1994, is used mainly in telecom equipment.
Zilog's fully pipelined Z80 compatible eZ80 with an 8/16/24-bit word length and a linear 16Â MB address space was introduced in 2001. It exists in versions with on chip SRAM or flash memory, as well as with integrated peripherals. One variant has on chip MAC (media access controller), and available software include a TCP/IP stack. In contrast with the Z800 and Z280, there are only a few added instructions (primarily LEAs, PEAs, and variable-address 16/24-bit loads), but instructions are instead executed between 2 and 11 times as clock cycle efficient as on the original Z80 (with a mean value around 3-5 times). It is currently specified for clock frequencies up to 50Â MHz.
Kawasaki developed the binary compatible KL5C8400 which is approximately 1.2-1.3 times as clock cycle efficient as the original Z80 and can be clocked at up to 33Â MHz. Kawasaki also produces the KL5C80A1x family, which has peripherals as well as a small RAM on chip; it is approximately as clock cycle efficient as the eZ80 and can be clocked at up to 10Â MHz (2006).
The NEC uPD9002 was an hybrid CPU compatible with both Z80 and x86 families.
The Chinese Actions Semiconductor's audio processor family of chips (ATJ2085 and others) contains a Z80-compatible MCU together with a 24-bit dedicated DSP processor. These chips are used in many MP3 and media player products.
The T80 (VHDL) and TV80 (Verilog) synthesizable soft cores are available from OpenCores.org.

Non-compatible

The Toshiba TLCS 900 series of high volume (mostly OTP) microcontrollers are based on the Z80; they share the same basic BC,DE,HL,IX,IY register structure, and largely the same instructions, but are not binary compatible, while the previous TLCS 90 is Z80-compatible.
The NEC 78K series microcontrollers are based on the Z80; they share the same basic BC,DE,HL register structure, and has similar (but differently named) instructions; not binary compatible.

Partly compatible

Rabbit Semiconductor's Rabbit 2000/3000/4000 microprocessors/microcontrollers are based on the HD64180/Z180 architecture, although they are not fully binary compatible.

No longer produced

The ASCII Corporation R800 was a fast 16-bit processor used in MSX TurboR computers; it was software, but not hardware compatible with the Z80 (signal timing, pinout & function of pins differ from the Z80).
Zilog's NMOS Z800 and CMOS Z280 were 16-bit Z80-implementations (before the HD64180 / Z180) with a 16Â MB paged MMU address space; they added many orthogonalizations and addressing modes to the Z80 instruction set. Minicomputer features â€" such as user and system modes, multiprocessor support, on chip MMU, on chip instruction and data cache and so on â€" were seen rather as more complexity than as functionality and support for the (usually electronics-oriented) embedded systems designer, it also made it very hard to predict instruction execution times.
Certain arcade games such as Pang/Buster Bros use an encrypted "Kabuki" Z80 CPU manufactured by VLSI Technology, where the decryption keys are stored in its internal battery-backed memory, to avoid piracy and illegal bootleg games.

Notable uses

A-Z80 CPU :: Overview :: OpenCores. Source : opencores.org

Desktop computers

During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system, a combination that dominated the market at the time. Four well-known examples of Z80+CP/M business computers are the portable Osborne 1, the Kaypro series, the Epson QX-10 and the Heathkit H89. Research Machines manufactured the 380Z and 480Z microcomputers which were networked with a thin Ethernet type LAN and CP/NET in 1981. Other manufacturers of such systems included Televideo, Xerox (820 range) and a number of more obscure firms. Some systems used multi-tasking operating system software (like MP/M) to share the one processor between several concurrent users.

In the U.S., the Radio Shack TRS-80, introduced in 1977, as well as the Models II, III, 4, and the proposed Model V, used the Z80. A number of TRS-80 clones were produced by companies like Lobo (Max-80), LNW (LNW-80), and Hong Kong-based EACA (Video Genie and derivatives TRZ-80, PMC-80, and Dick Smith System 80). In the Netherlands a TRS-80 Model III clone was produced that had CP/M capability; this was the Aster CT-80. In the United Kingdom, Sinclair Research used the Z80 and Z80A in its ZX80, ZX81, and ZX Spectrum home computers. These were marketed in the USA by Timex as the Timex/Sinclair series. Amstrad used the Z80A in their Amstrad CPC and PCW ranges and an early UK computer, the Nascom 1 and 2 also used it. The Z80 powered a great many home computers adhering to the MSX standard in Japan, Asia, and to a lesser extent, Europe and South America (some 5 million in Japan alone). Also in Japan Sharp used the Z80 in its MZ and X1 series. In Germany an Apple-CP/M hybrid called the Base 108 paired a Z80 with a 6502. Similarly the Commodore 128 featured a Z80 processor alongside its MOS Technology 8502 processor for CP/M compatibility. Other 6502 architecture computers on the market at the time, such as the BBC Micro, Apple II, and the 6510 based Commodore 64, could make use of the Z80 with an external unit, a plug-in card, or an expansion ROM cartridge. The Microsoft Z-80 SoftCard for the Apple II was a particularly successful add-on card and one of Microsoft's few hardware products of the era.

In 1981, Multitech (later to become Acer) introduced the Microprofessor I, a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still manufactured and sold by Flite Electronics International Limited in Southampton, England.

Embedded systems and consumer electronics

The Zilog Z80 has long been a popular microprocessor in embedded systems and microcontroller cores, where it remains in widespread use today. The following list provides examples of such applications of the Z80, including uses in consumer electronics products.

Industry

The IBM PC-XT's hard drive controller, which was actually an IBM adaptation of the Xebec 1410 SASI controller, but on a PC-XT bus, not a SASI bus.
Office equipment such as matrix printers, fax machines, answering machines, and photocopiers are known examples. The original Hewlett-Packard Deskjet printer used a Z180.
Industrial programmable logic controllers (PLCs) use the Z80 in CPU modules, for auxiliary functions such as analog I/O, or in communication modules.
It has also been employed in robots, for example for speech recognition and low level tasks such as servo processors in pick and place machines.
RS-232 multiplexers connecting large numbers of old style "terminals" to minicomputers or mainframes used arrays of Z80 CPU/SIO boards.
Applications such as TV broadcast vision mixers have used the Z80 for embedded real time subtasks.
It has also been used in Seagate Technology's and other manufacturers' hard disks.
Credit card consoles controlling fuel pumps used Z80 CPU and PIOs (US patents 4930665, 4962462 and 5602745).
Retail industry point-of-sale credit card terminals manufactured by VeriFone used the Z80 processor.
Several PC expansion cards, such as Adaptecs SCSI boards, have been using the Z80/Z180 and peripheral chips.
Z80/Z180/Z380 have been used in telecommunication equipment such as telephone switches and various kinds of modems.
The Stofor message switch, used extensively by banks and brokers in the UK was Z80 based.
Cash registers and store management systems
Home automation, wireless sprinkler control and wireless mesh using the N8VEM open source homebrew system.
Breathalyzer equipment used by law enforcement agencies.

Consumer electronics

The Amstrad NC100/NC200 and Cambridge Z88 notebook computers made in the United Kingdom used the Z80.
Amstrad in the UK produced an early PDA called the PenPad, or PDA600, which was built around a 14Â MHz Z180.
Z80 was often used in coin-operated arcade games, and was commonly used as the main CPU, sound or video coprocessors. Pac-Man arcade games feature a single Z80 as the main CPU, and Frogger used two Z80 CPUs. Galaxian and arcade games such as King & Balloon and Check Man that use the Namco Galaxian boardset also use a Z80 as the main CPU. Other Namco licensed arcade games such as Galaga and other games that use the Namco Galaga boardset such as Bosconian, Dig Dug, Xevious, and Super Xevious use three Z80 microprocessors running in parallel for the main CPU, graphics, and sound. Later Sega System 16, 18, X, and Y; Capcom CPS1 and CPS2; SNK Neo Geo MVS use 68000 and Z80 combination as co processors or sound CPUs.
It was also found in home video game consoles such as the ColecoVision, Sega Master System and Sega Game Gear video game consoles, as an audio and general-purpose co-processor in the Sega Genesis and as an audio controller and co-processor to the Motorola 68000 in the SNK Neo-Geo.
Nintendo's Game Boy and Game Boy Color handheld game systems used an 8080-derived processor with some Z80 instructions added (CB prefix) as well as unique auto-increment/decrement addressing modes. The CPU was a Sharp Corporation LR35902 running at 4.19Â MHz in the original and Pocket models, and 8.39Â MHz in the Color model. This processor was later included in the Game Boy Advance / SP / Micro taking up a new role as a co-processor for backwards compatibility with Game Boy / Color games (except Micro) and to add legacy 8-bit sounds to supplement the digital samples in Game Boy Advance games.
In Russia, Z80 and its clones were widely used in multi-functional land line phones with Caller ID.
Various scientific and graphing calculators use the Z80, including the Texas Instruments TI-73, TI-81, TI-82, TI-83, TI-83+, TI-84+, TI-85 and TI-86 series.
The Ericsson GA628 mobile phone uses the Z80 CPU.
All the S1 MP3 Player type digital audio players use the Z80 instruction set.

Musical instruments

MIDI sequencers such as E-mu 4060 Polyphonic Keyboard and Sequencer, Zyklus MPS, and Roland MSQ700 were built around the Z80.
MIDI controllers and switches such as Waldorf Midi-Bay MB-15 and others.
Several polyphonic analog synthesizers used it for keyboard-scanning (also wheels, knobs, displays...) and D/A or PWM control of analog levels; in newer designs, sometimes sequencing or MIDI-communication. The Z80 was also often involved in the sound generation itself, implementing LFOs, envelope generators and so on. Known examples include:
- Sequential Circuits Prophet 5, Prophet 10, Prophet T8, Prophet 600, Six-Trak, Multitrak, MAX, and Split-8
- MemoryMoog six-voice synthesizer
- Oberheim OB-8 eight-voice synthesizer with MIDI
- Roland Jupiter-8 eight-voice synthesizer
- VEM Tiracon 6V six-voice analog synthesizer (1987) with U880 CPU from East Germany (Deutsche Demokratische Republik)
Digital sampling synthesizers such as the Emulator I, Emulator II, and Akai S700 12-bit Sampler, as well as drum machines like the E-mu SP-12, E-mu SP-1200, E-mu Drumulator, and the Sequential Circuits Drumtraks, used Z80 processors.
Many Lexicon reverberators (PCM70, LXP15, LXP1, MPX100) used one or more Z80s for user interface and LFO generation where dedicated hardware provided DSP functions.
The ADA MP-1 and Digitech GSP 2101/2112/2120, MIDI controlled, vacuum tube, guitar pre-amplifiers.

Footnotes

Thomas Scherrer Z80-Family Official Support Page. Source : www.z80.info

References

Z80 Computer and Assembler Adventures - Jack's Projects and Notes. Source : www.crepinc.com

"Sharp LH0080 Z80 CPU Reference Manual" (pdf). Abeno-ku, Osaka, Japan: Sharp Corporation. Retrieved 2009-07-15.Â

External links

Zilog Z80 Product Family
Z80-Family Official Support Page
Z80 software emulators
Yet Another Z80 Emulator by AG (YAZE-AG)
DEEDS - Digital Electronics Education and Design Suite - Simulators for Digital Design Training - The suite covers also microprocessor systems based on the DMC8 (an 8 bit CPU derived from Z80), and exports projects in VHDL and on FPGA (free download)
Flite Electronics: Manufacturer of the Z80 Microprofessor Training System
Free Z80 CPU core (VHDL code), (Verilog code)
The Undocumented Z80 Documented
N8VEM SBC
mdfs.net: Z80 opcode list
zilog Z80 CPU User Manual hosted by Let's Hack Arcade Games
Mostek Z80 Processor Technical Manual
Sharp LH0080 at CPU World
Z80 Bus Emulator for education purpose. Includes NEC's TK-80 Training-Kit-, ZX-80 Microcomputer-, CP/M 2.2 Emulator.
How the Z80's registers are implemented in silicon
ZED Computer - Single Board Computer
RC2014 Modern Z80 DIY kit
The Z80 Membership Card DIY kit
CPUville Z80 DIY kit

Zilog Z80 - Z80 Computer

Sunday, March 4, 2018

Zilog Z80 - Z80 Computer

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